| Specifications |
| Peripherals |
Quantity |
Description |
| FPGA chip |
1 |
XC6SLX16-2FTG256C(FBGA256), Speed Grade 2, Logic Elements 14579, Memory Bits 576Kb, Embedded Multipliers DSP48 16, Global Clocks 2 |
| SDRAM |
1 |
One piece of 16M×16Bit SDRAM, maximum 166MHz read and write speed 256Mb, large capacity, independent I/O control, independent data address bus. |
| Serial configuration FLASH |
1 |
Standard M25P16 (16Mbit), programming firmware or embedded programs and user data. |
| QSPI FLASH |
1 |
A 128Mbit Quad-SPI FLASH chip is used to store user data or files, the chip model is W25Q128. A 128Mbit Quad-SPI FLASH chip is used to store user data or files. |
| EEPROM |
1 |
A piece of EEPROM, the model is 24LC04, the capacity is: 4Kbit (2*256*8bit) |
| TF/SD card holder |
1 |
Provide a standard TF card slot, support FAT16, FAT32 data format storage |
| USB to Serial |
1 |
Through the commonly used CH340 USB to serial port chip, users can use a USB cable to connect it to the USB port of the PC for serial data communication |
| USB2.0 |
1 |
>High-speed data communication between PC and FPGA is realized through Cypress CY7C68013A USB2.0 controller chip, which supports low-speed (12Mbit/s) and full-speed (480Mbit/s) modes. And provide independent reset button, and firmware independent shield jumper, which is convenient for users to independently develop USB2.0 interface |
| clock |
1 |
An active clock of 50M, users can change other frequencies by themselves, and can also use the IFCLK and CLKOUT of the USB2.0 chip 68013 as the clock |
| Real Time Clock |
1 |
The real-time clock RTC chip, model DS1302, its function is to provide the calendar function until 2099, the year, month, day, hour, minute, second, and week. And reserve the battery interface, connect the standard notebook battery, can realize long-term clock accurate time travel. |
| key switch |
5 |
With pull-up potential, user key input. |
| power supply |
3 |
5V, 3.3V/2A, 1.2V/800MA independent leads are convenient for users to use and test |
| JTAG port |
1 |
Debug the FPGA online, and solidify the user program and firmware. Standard 2*7 14PIN 2.0MM pitch socket |
| LVDS |
8 |
The independent 8 pairs of LVDS are led out from J6 BANK0, and different level standards can be selected by adjusting the voltage of BANK0. The independent LDO power supply chip, the default 3.3V IO level. |
| led |
6 |
4 independent IO interface LEDS, users can define by themselves, 2 RXD/TXT status indication |
| System Master Reset |
1 |
System reset button, with pull-up. It can also be used as user key input. |
| PCB routing |
|
High-speed 4-layer PCB wiring, manual wiring by senior engineers, and isometric EMC simulation analysis to ensure high-speed operation of the system. Size: (85mm X 82mm) |
| PMOD interface |
1 |
XILINX PMOD standard interface, equal-length wiring and EMC simulation analysis. Can be directly connected to various PMOD modules of XILINX |
| Expansion I/O |
3 |
Expand the IO interface for sampling equal-length wiring, and perform high-speed EMC simulation analysis to ensure that the interface is connected to external devices at high speed. (J6)38+(J7)38+(J1)8=84 (extract independent I/O). Among them, the two expansion IOs of J6 and J7 are interchangeable and compatible with our various expansion modules, and J1 is the XILINX PMOD standard interface. Can be directly connected to various PMOD modules of XILINX |
