SoC
- Xilinx XC7Z015-1CLG485C (Zynq-7015)
- 667MHz ARM® dual-core Cortex™-A9 MPCore processor (up to 866MHz)
- Integrated Artix-7 class FPGA subsystem with 74K logic cells, 46,200 LUTs, 160 DSP slices
- NEON™ & Single / Double Precision Floating Point for each processor
- Supports a Variety of Static and Dynamic Memory Interfaces
- Four high-speed SerDes transceivers up to 6.25Gbps
- Four PCIe Gen2 hardened, integrated IP blocks
Memory
- 1GB DDR3 SDRAM (512MB*2)
- 4GB eMMC
- 32MB QSPI Flash (16MB is optional)
Peripherals and Signals Routed to Pins
- One10/100/1000M Ethernet PHY
- One USB PHY
- External watchdog
- Three LEDs
- One blue LED for power indicator
- One red LED for FPGA program done indicator
- One green user LED
- Two 0.8mm pitch 140-pin board-to-board expansion connectors bring out below signals:
- One Gigabit Ethernet (PS Ethernet 0)
- One USB OTG 2.0 (PS USB 0)
- Up to two Serial ports (reused from PS_MIO, can also be implemented through PL pins)
- Up to two I2C (reused from PS_MIO, can also be implemented through PL pins)
- Up to two CAN BUS (reused from PS_MIO, can also be implemented through PL pins)
- One SPI (reused from PS_MIO, can also be implemented through PL pins)
- ADC (one independent differential ADC, 16-channel ADC brought out through PL pins)
- One SDIO (PS SDIO 0)
- Bank 13 (PL I/O configurable as up to 18 LVDS pairs and 1 single-ended I/O or 37 single-ended I/O)
- Bank 34 (PL I/O configurable as up to 24 LVDS pairs and 2 single-ended I/O or 50 single-ended I/O)
- Bank 35 (PL I/O configurable as up to 24 LVDS pairs and 2 single-ended I/O or 50 single-ended I/O)
- Bank 112 (4 GTP serial transceivers, 2 reference clock input)
